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fedl610403-04 issue date: may.23, 2014 ML610401/ml610402/ml610403 8-bit microcontroller with a built-in lcd driver 1/27 general description ML610401/ml610402/ml610403 is a high-performance 8-bit cmos microcontroller into which peripheral circuits, such as uart,melody driver, rc oscillation type a/d converter, and lcd driver, are incorporated around lapis semiconductor original 8-bit cpu nx-u8/100. ML610401/ml610402/ml610403 operates in both high/low-speed mode and power-saving mode, it is most suitable for battery operated products. ML610401p/ ml610402p/ml610403p support industrial temperature -40 c to +85 c, are added to the product lineup. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? minimum instruction execution time 30.5 s (@32.768 khz system clock) 2 s (@500khz system clock) ? internal memory ? internal 6kbyte mask rom (3k 16 bits) (including unusable 256 byte test area) ? internal 192byte data ram (192 8 bits) ? interrupt controller ? 1 non-maskable interrupt sources internal source: 1 (watch dog timer) ? 17 maskable interrupt sources internal sources: 9 (timer2, timer3, uart0, melody0, rc-a/d converter, tbc128hz, tbc32hz, tbc16hz, tbc2hz) external sources: 8 (p00, p01, p02, p03, p50, p51, p52, p53) (one interrupt request is generated from p50 to p53 interrupt sources.) ? time base counter ? low-speed time base counter 1 channel frequency compensation (compensation range: approx. ? 488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) ? high-speed time base counter 1 channel ? watchdog timer ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timers ? 8 bits 2 channels (16-bit x 1 configuration available by using timer2-3) ? clock frequency measurement mode (in one channel of 16-bit configuration) ? capture ? time base capture 2 channels (4096 hz to 32 hz)
fedl610403-04 ML610401/ml610402/ml610403 2/27 ? uart ? txd/rxd 1 channel ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? melody driver ? scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) ? tone length: 63 types ? tempo: 15 types ? buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) ? rc oscillation type a/d converter ? 16-bit counter ? time division 2 channels ? general-purpose ports ? input-only port 4 channels (including secondary functions) ? output-only port ML610401: 12 channels (including secondary functions) ml610402: 8 channels (including secondary functions) ml610403: 4 channels (including secondary functions) ? input/output port 18 channels (including secondary functions) ? lcd driver ? the number of segments ML610401: 55 dots max. (11seg 5com, 12seg 4com, 13seg 3com, and 14seg 2com selectable) ml610402: 75 dots max. (15seg 5com, 16seg 4com, 17seg 3com, and 18seg 2com selectable) ml610403: 95 dots max. (19seg 5com, 20seg 4com, 21seg 3com, and 22seg 2com selectable) ? 1/1 to 1/5 duty ? 1/3 bias (built-in bias generation circuit) ? frame frequency selecable: approx. 64hz, 73hz, 85hz, and 102hz ? bias voltage multiplying clock selectable (8 types) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? programmable display allocation function ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset when oscillation stop of the low-speed clock is detected (cancellation by a mask option is possible) ? reset by the watchdog timer (wdt) overflow ? clock ? low-speed clock: crystal oscillation (32.768 khz) (this lsi can not guarantee the operation withoug low-speed crystal oscillation clock) ? high-speed clock: built-in rc oscillation (500 khz) ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the oscillation clock) ? block control function: resets and completely turns circuits of unused peripherals off.
fedl610403-04 ML610401/ml610402/ml610403 3/27 ? guaranteed operating range ? operating temperature: ? 20 c to +70 c (p version: ?40 c to +85 c) ? operating voltage: v dd = 1.25v to 3.6v ? product name ? s upported function lcd bias - chip (die) - 1/2 1/3 low-speed oscillation stop detect reset operating temperature product availability ML610401- wa - yes cancellation by a mask option is p ossible -20c to +70c yes ml610402- wa - yes cancellation by a mask option is possible -20c to +70c yes ml610403- wa - yes cancellation by a mask option is possible -20c to +70c yes ML610401p- wa - yes cancellation by a mask option is possible -40c to +85c yes ml610402p- wa - yes cancellation by a mask option is possible -40c to +85c yes ml610403p- wa - yes cancellation by a mask option is possible -40c to +85c yes lcd bias -64-pin plastic tqfp - 1/2 1/3 low-speed oscillation stop detect reset operating temperature product availability ML610401- tb - yes cancellation by a mask option is p ossible -20c to +70c - ml610402- tb - yes cancellation by a mask option is possible -20c to +70c - ml610403- tb - yes cancellation by a mask option is possible -20c to +70c - ML610401p- tb - yes cancellation by a mask option is possible -40c to +85c - ml610402p- tb - yes cancellation by a mask option is possible -40c to +85c ml610403p- tb - yes cancellation by a mask option is possible -40c to +85c - xxx: rom code number p: wide range temperature version wa: chip tb: tqfp
fedl610403-04 ML610401/ml610402/ml610403 4/27 block diagram ML610401/ml610402/ml610403 block diagram figure 1 show the block diagram of the ML610401/ml610402/ml610403. "*" indicates the secondary function of each port. " (*1) " 11seg5com, 12seg4com, 13seg3com, and 14seg2com selectable " (*2) " 15seg5com, 16seg4com, 17seg3com, and 18seg2com selectable " (*3) " 19seg5com, 20seg4com, 21seg3com, and 22seg2com selectable figure 1 ML610401/ml610402/ml610403 block diagram timing controller ea sp instruction decoder bus controller instruction register capture 2 int 2 8bit timer 2 data-bus test0 reset_n xt0 xt1 lsclk* outclk* power v ddl lcd driver com0 to com4 ( *1 )( *2 )( *3 ) seg0 to seg13 (ML610401) (*1) seg0 to seg17 (ml610402) (*2) seg0 to seg21 ( ml610403 ) ( *3 ) lcd bias v l1 , v l2 , v l3 c1 , c2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss int 1 display register 176bit display allocation ram gpio int 5 p00 to p03 p20 to p22 , p24 p30 to p35 p40 to p47 p50 to p53 p60 to p67 (ML610401) p60 to p63 (ml610402) int 1 md0* melody/ buzzer rxd0* txd0* int 1 uart wdt int 1 tbc int 4 interrupt controller ram 192byte rc-adc 2 osc program memory (rom) 6kbyte cpu (nx-u8/100)
fedl610403-04 ML610401/ml610402/ml610403 5/27 pin configuration ML610401 chip pin layout & dimension 31 seg11 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 48 p01 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 p02 p03 p30 p31 p34 p32 p33 p35 p53 p52 p51 p50 p40 p41 p42 1 6 5 4 2 3 7 8 9 10 11 1 2 1 3 14 15 p4 3 v dd p47 p4 6 p44 p45 v ss v ddl xt0 xt1 reset_n test 0 v l1 v l2 v l3 47 42 4 3 44 4 6 45 41 4 0 39 38 3 7 36 35 3 4 3 2 33 p00 v ss p2 0 p21 p24 p22 p6 0 p61 p62 p6 3 p6 4 p65 p66 p6 7 seg12 seg13 1.75mm 1.82mm x y note: the assignment of the pads p30 to p35 are not in order. chip size: 1.82 mm 1.75 mm pad count: 63 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 5 ML610401 chip layout & dimension
fedl610403-04 ML610401/ml610402/ml610403 6/27 ml610402 chip pin layout & dimension 31 seg11 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 48 p01 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 p02 p03 p30 p31 p34 p32 p33 p35 p53 p52 p51 p50 p40 p41 p42 1 6 5 4 2 3 7 8 9 10 11 1 2 1 3 14 15 p4 3 v dd p47 p4 6 p44 p45 v ss v ddl xt0 xt1 reset_n test 0 v l1 v l2 v l3 47 42 4 3 44 4 6 45 41 4 0 39 38 3 7 36 35 3 4 3 2 33 p00 v ss p2 0 p21 p24 p22 p6 0 p61 p62 p6 3 seg17 seg16 seg15 seg14 seg12 seg13 1.75mm 1.82mm x y note: the assignment of the pads p30 to p35 are not in order. chip size: 1.82 mm 1.75 mm pad count: 63 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 6 ml610402 chip layout & dimension
fedl610403-04 ML610401/ml610402/ml610403 7/27 ml610403 chip pin layout & dimension 31 seg11 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 48 p01 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 p02 p03 p30 p31 p34 p32 p33 p35 p53 p52 p51 p50 p40 p41 p42 1 6 5 4 2 3 7 8 9 10 11 1 2 1 3 14 15 p4 3 v dd p47 p4 6 p44 p45 v ss v ddl xt0 xt1 reset_n test 0 v l1 v l2 v l3 47 42 4 3 44 4 6 45 41 4 0 39 38 3 7 36 35 3 4 3 2 33 p00 v ss p2 0 p21 p24 p22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg12 seg13 1.75mm 1.82mm x y note: the assignment of the pads p30 to p35 are not in order. chip size: 1.82 mm 1.75 mm pad count: 63 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 7 ml610403 chip layout & dimension
fedl610403-04 ML610401/ml610402/ml610403 8/27 ML610401/ml610402/ml610403 pad coordinates table 1 ML610401/ml610402/ml610403 pad coordinates chip center: x=0,y=0 ML610401/2/3 ML610401/2/3 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 p43 -598 -769 p66 (*1) 2 p44 -518 -769 35 seg15 (*2)(*3) 375 769 3 p45 -438 -769 p65 (*1) 4 p46 -358 -769 36 seg16 (*2)(*3) 295 769 5 p47 -278 -769 p64 (*1) 6 v dd -198 -769 37 seg17 (*2)(*3) 215 769 7 v ss -118 -769 p63 (*1)(*2) 8 v ddl -38 -769 38 seg18 (*3) 135 769 9 xt0 42 -769 p62 (*1)(*2) 10 xt1 202 -769 39 seg19 (*3) 55 769 11 reset_n 282 -769 p61 (*1)(*2) 12 test0 362 -769 40 seg20 (*3) -25 769 13 vl1 522 -769 p60 (*1)(*2) 14 vl2 602 -769 41 seg21 (*3) -105 769 15 vl3 682 -769 42 v ss -185 769 16 c1 804 -600 43 p20 -265 769 17 c2 804 -520 44 p21 -345 769 18 com0 804 -440 45 p22 -425 769 19 com1 804 -360 46 p24 -505 769 20 com2/seg0 804 -280 47 p00 -605 769 21 com3/seg1 804 -200 48 p01 -804 600 22 com4/seg2 804 -120 49 p02 -804 520 23 seg3 804 -40 50 p03 -804 440 24 seg4 804 40 51 p30 -804 360 25 seg5 804 120 52 p31 -804 280 26 seg6 804 200 53 p34 -804 200 27 seg7 804 280 54 p32 -804 120 28 seg8 804 360 55 p33 -804 40 29 seg9 804 440 56 p35 -804 -40 30 seg10 804 520 57 p53 -804 -120 31 seg11 804 600 58 p52 -804 -200 32 seg12 645 769 59 p51 -804 -280 33 seg13 565 769 60 p50 -804 -360 p67 (*1) 61 p40 -804 -440 34 seg14 (*2)(*3) 455 769 62 p41 -804 -520 63 p42 -804 -600 (*1) ML610401 pad name, (*2) ml610402 pad name, (*3) ml610403 pad name
fedl610403-04 ML610401/ml610402/ml610403 9/27 pin list primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 7,43 7,42 vss ? negative power supply pin ? ? ? 6 6 v dd ? positive power supply pin ? ? ? 8 8 v ddl ? power supply pin for internal logic (internally generated) ? ? ? 14 13 v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? 15 14 v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? 16 15 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? 17 16 c1 ? capacitor connection pin for lcd bias generation ? ? ? 18 17 c2 ? capacitor connection pin for lcd bias generation ? ? ? 13 12 test0 i test pin ? ? ? 12 11 reset_n i reset input pin ? ? ? 10 9 xt0 i low-speed clock oscillation pin ? ? ? 11 10 xt1 o low-speed clock oscillation pin ? ? ? 48 47 p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? 49 48 p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? 50 49 p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? 51 50 p03/exi3 i input port, external interrupt ? ? ? 44 43 p20/led0 o output port lscl k o low-speed clock output 45 44 p21/led1 o output port outc lk o high-speed clock output 46 45 p22/led2 o output port md0 o melody 0 output 47 46 p24/led4 o output port ? ? ? 52 51 p30 i/o input/output port in0 i rc type adc0 oscillation input pin 53 52 p31 i/o input/output port cs0 o rc type adc0 reference capacitor connection pin 54 53 p34 i/o input/output port rct0 o rc type adc0 resistor/capacitor sensor connection pin 55 54 p32 i/o input/output port rs0 o rc type adc0 reference resistor connection pin 56 55 p33 i/o input/output port rt0 o rc type adc0 measurement resistor sensor connection pin 57 56 p35 i/o input/output port rcm o rc type adc oscillation monitor 62 61 p40 i/o input/output port ? ? ? 63 62 p41 i/o input/output port ? ? ? 64 63 p42 i/o input/output port rxd0 i uart data input 1 1 p43 i/o input/output port txd0 o uart data output 2 2 p44/t2ck i/o input/output port, timer2 external clock input in1 i rc type adc1 oscillation input pin 3 3 p45/t3ck i/o input/output port, timer3 external clock input cs1 o rc type adc1 reference capacitor connection pin 4 4 p46 i/o input/output port rs1 o rc type adc1 reference resistor connection pin 5 5 p47 i/o input/output port rt1 o rc type adc1 measurement resistor sensor connection pin 61 60 p50/exi8 i/o input/output port, external interrupt md0 o melody 0 output 60 59 p51/exi8 i/o input/output port, external interrupt ? ? ? 59 58 p52/exi8 i/o input/output port, external interrupt ? ? ?
fedl610403-04 ML610401/ml610402/ml610403 10/27 primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 58 57 p53/exi8 i/o input/output port, external interrupt ? ? ? 19 18 com0 o lcd common pin ? ? ? 20 19 com1 o lcd common pin ? ? ? 21 20 com2/seg0 o lcd common/segment pin ? ? ? 22 21 com3/seg1 o lcd common/segment pin ? ? ? 23 22 com4/seg2 o lcd common/segment pin ? ? ? 24 23 seg3 o lcd segment pin ? ? ? 25 24 seg4 o lcd segment pin ? ? ? 26 25 seg5 o lcd segment pin ? ? ? 27 26 seg6 o lcd segment pin ? ? ? 28 27 seg7 o lcd segment pin ? ? ? 29 28 seg8 o lcd segment pin ? ? ? 30 29 seg9 o lcd segment pin ? ? ? 31 30 seg10 o lcd segment pin ? ? ? 32 31 seg11 o lcd segment pin ? ? ? 33 32 seg12 o lcd segment pin ? ? ? 34 33 seg13 o lcd segment pin ? ? ? p67 (*4) o output port ? ? ? 35 34 seg14 (*5) o lcd segment pin ? ? ? p66 (*4) o output port ? ? ? 36 35 seg15 (*5) o lcd segment pin ? ? ? p65 (*4) o output port ? ? ? 37 36 seg16 (*5) o lcd segment pin ? ? ? p64 (*4) o output port ? ? ? 38 37 seg17 (*5) o lcd segment pin ? ? ? p63 (*2) o output port ? ? ? 39 38 seg18 (*3) o lcd segment pin ? ? ? p62 (*2) o output port ? ? ? 40 39 seg19 (*3) o lcd segment pin ? ? ? p61 (*2) o output port ? ? ? 41 40 seg20 (*3) o lcd segment pin ? ? ? p60 (*2) o output port ? ? ? 42 41 seg21 (*3) o lcd segment pin ? ? ? (*1) internally generated, or connect to either positive power supply pin (v dd ) or power supply pin for internal logic (v ddl ). for details, see user?s manual. (*2) pin for ML610401/ml610402. (*3) pin for ml610403. (*4) pin for ML610401. (*5) pin for ml610402/ml610403.
fedl610403-04 ML610401/ml610402/ml610403 11/27 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across this pin and v ss . ? ? lsclk o low-speed clock output pin. this pin is used as the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00-p03 i general-purpose input port. primary positive general-purpose output port p20-p22,p24 o general-purpose output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose input/output port p30-p35 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p40-p47 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p50-p53 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p60-p63 o general-purpose output port. these pins are for the ML610401/ml610402, but are not provided in the ml610403. primary positive p64-p67 o general-purpose output port. these pins are for the ML610401, but are not provided in the ml610402/ml610403. primary positive
fedl610403-04 ML610401/ml610402/ml610403 12/27 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/ secondary positive external interrupt exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00-p03 pins. primary positive/ negative exi8 external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p50-p53 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t2ck i external clock input pin used for timer 2. the clock for this timer is selected by software. this pin is used as the primary function of the p44 pin. primary ? t3ck i external clock input pin used for timer 3. the clock for this timer is selected by software. this pin is used as the primary function of the p45 pin. primary ? melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p22 pin and p50 pin. secondary positive/ negative led drive led0-2,4 o nch open drain output pins to drive led. primary positive/ negative
fedl610403-04 ML610401/ml610402/ml610403 13/27 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin is used as the secondary function of the p31 pin. secondary ? rct0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? rs0 o this pin is used as the secondary function of the p32 pin which is the reference resistor connection pin of channel 0. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? lcd drive signal com0-4 o common output pins. ? ? seg0-13 o segment output pins. ? ? seg14-17 o segment output pin. these pins are for the ml610402/ml610403, but are not provided in the ML610401. ? ? seg18-21 o segment output pin. these pins are for the ml610403, but are not provided in the ML610401/ml610402. ? ? lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pins for lcd bias (internally generated or positive power supply pin connected ). depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. for details of the connection method, see user?s manual. ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitors c12 is connected between c1 and c2. ? ? for testing test0 i/o input/output pin for testing. a pull-down resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin for i/o, internal regulator, battery low detector, and power-on reset. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitor cl (see appendix c measuring circuit 1) is connected between this pin and v ss . ? ?
fedl610403-04 ML610401/ml610402/ml610403 14/27 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin termination v l1 , v l2 , v l3 open c1, c2 open reset_n open test0 open p00 to p03 v dd or v ss p20 to p22, p24 open p30 to p35 open p40 to p47 open p50 to p53 open p60 to p67 open com0 to com4 open seg0 to seg21 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610403-04 ML610401/ml610402/ml610403 15/27 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to +4.6 v power supply voltage 2 v ddl ta = 25 c ? 0.3 to +3.6 v power supply voltage 3 v l1 ta = 25 c ? 0.3 to +2.0 v power supply voltage 4 v l2 ta = 25 c ? 0.3 to +4.0 v power supply voltage 5 v l3 ta = 25 c ? 0.3 to +6.0 v input voltage v in ta = 25 c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port3?6, ta = 25 c ? 12 to +11 ma output current 2 i out2 port2, ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 0.9 w storage temperature t stg ? ? 55 to +150 c recommended operat ing conditions (v ss = 0v) parameter symbol condition range unit non-p version ? 20 to +70 operating temperature t op p version ? 40 to +85 c operating voltage v dd f op = 30k to 625khz 1.25 to 3.6 v operating frequency (cpu) f op v dd = 1.25 to 3.6v 30k to 625k hz capacitor externally connected to v dd pin c v ? 1.030% to 2.230%* 1 f capacitor externally connected to v ddl pin c l ? 0.47 30% to 2.230%* 2 f capacitors externally connected to v l1, 2, 3 pins c a, b, c ? 0.1 30% f capacitors externally connected across c1 and c2 pins c 12 ? 0.47 30% f * 1 : please select c v as to be larger than c l or same as c l . * 2 : when the load of v dd is small and the power rise time is too short, it may happen that the power-on reset is not generated. in this case, please select larger capacitance value for c l . clock generation circuit operating conditions (v ss = 0v) rating parameter symbol condition min. typ. max. unit low-speed crystal oscillation frequency f xtl ? ? 32.768k ? hz recommended equivalent series resistance value of low-speed crystal oscillation r l ? ? ? 40k ? c l =6pf of crystal oscillation ? 12 ? c l =9pf of crystal oscillation ? 18 ? low-speed crystal oscillation external capacitor c dl /c gl c l =12pf of crystal oscillation ? 24 ? pf
fedl610403-04 ML610401/ml610402/ml610403 16/27 dc characteristics (1/5) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 c typ. ? 10% 500 typ. + 10% 500khz rc oscillation frequency f rc v dd = 1.25 to 3.6v * 3 typ. ? 25% 500 typ. + 25% khz low-speed crystal oscillation start time* 2 t xtl ? ? 0.6 2 s 500khz rc oscillation start time t rc ? ? ? 3 s low-speed oscillation stop detect time *1 t stop ? 12 16.4 41 ms reset pulse width p rst ? 200 ? ? reset noise elimination pulse width p nrst ? ? ? 0.3 s power-on reset activation power rise time t por ? ? ? 10 ms 1 * 1 : when low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf). * 3 : recommended operating temperature (ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version) reset_n reset pulse width (p rst ) vdd 0.9xv dd 0.1xv dd t por powe r -on reset activation power rise time (t por ) p rst vil1 vil1
fedl610403-04 ML610401/ml610402/ml610403 17/27 dc characteristics (2/5) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit v ddl voltage v ddl f op = 30k to 625khz 1.1 1.2 1.3 v v ddl temperature deviation * 1 ? v ddl v dd = 3.0v ? -1 ? mv/ c v ddl voltage dependency * 1 ? v ddl ? ? 5 20 mv/v 1 * 1 :v ddl can not exceed v dd level. the maximum v ddl becomes v dd level when the v ddl calculated by the temperature deviation and voltage dependency is going to exceed the v dd level.
fedl610403-04 ML610401/ml610402/ml610403 18/27 dc characteristics (3/5) (v dd = 3.0v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version) rating parameter symbol condition min. typ. max. unit measuring circuit ta= 25 c ? 0.3 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed rc500khz oscillation: stopped. * 5 ? ? 3 a ta= 25 c ? 0.9 1.8 supply current 2 idd2 cpu: in halt state (ltbc and wdt are operating).* 3 * 4 high-speed 500khz oscillation: stopped. lcd and bias circuits: operating. * 6 * 5 ? ? 4 a ta= 25 c ? 3 6 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz oscillation: stopped. lcd and bias circuits: operating. * 2 * 5 ? ? 9 a ta= 25 c ? 50 70 supply current 4 idd4 cpu: in rc 500khz operating state. lcd and bias circuits: operating. * 2 * 5 ? ? 80 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock: 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 4 : significant bits of blkcon0~blkcon4 registers except dlcd bit on blkcon4 are all ?1?. * 5 : recommended operating temperature (ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz)
fedl610403-04 ML610401/ml610402/ml610403 19/27 dc characteristics (4/5) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ? voh1 ioh1 = -0.03ma, v dd = 1.25 to 3.6v v dd ? 0.3 ? ? iol1 = +0.5ma, v dd = 1.8 to 3.6v ? ? 0.5 output voltage 1 (p20?p22,p24/ 2 nd function is selected) (p30?p35) (p40?p47) (p50?p53) (p60-p63) *1 *2 (p64-p67) *1 vol1 iol1 = +0.1ma, v dd = 1.25 to 3.6v ? ? 0.3 output voltage 2 (p20?p22,p24/ 2 nd function is not selected) vol2 iol2 = +5ma, v dd = 1.8 to 3.6v ? ? 0.5 voh3 ioh3 = ? 0.05ma, vl1=1.2v v l3 ? 0.2 ? ? vomh3 iomh3 = +0.05ma, vl1=1.2v ? ? v l2 +0.2 vomh3s iomh3s = ? 0.05ma, vl1=1.2v v l2 ? 0.2 ? ? voml3 ioml3 = +0.05ma, vl1=1.2v ? ? v l1 +0.2 voml3s ioml3s = ? 0.05ma, vl1=1.2v v l1 ? 0.2 ? ? output voltage 3 (com0?4) (seg0?13) *1 (seg0?17) *2 (seg0?21) *3 vol3 iol3 = +0.05ma, vl1=1.2v ? ? 0.2 v 2 iooh voh = v dd (in high-impedance state) ? ? 1 output leakage (p20?p22, p24) (p30?p35) (p40?p47) (p50?p53) (p60-p63) *1 *2 (p64-p67) *1 iool vol = v ss (in high-impedance state) ? 1 ? ? a 3 iih1 vih1 = v dd 0 ? 1 input current 1 (reset_n) iil1 vil1 = v ss -600 -300 -2 iih2 vih2 = v dd 2 300 600 input current 2 (test0) iil2 vil2 = v ss -1 ? ? vih3 = v dd ,v dd = 1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3 = v dd ,v dd = 1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3 = v ss , v dd = 1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3 = v ss , v dd = 1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3 = v dd (in high-impedance state) ? ? 1 input current 3 (p00-p03) (p30-p35) (p40-p47) (p50-p53) iil3z vil3 = v ss (in high-impedance state) ? 1 ? ? a 4 * 1 : pins for ML610401 * 2 : pins for ml610402 * 3 : pins for ml610403
fedl610403-04 ML610401/ml610402/ml610403 20/27 dc characteristics (5/5) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit vih1 ? 0.7 v dd ? v dd v dd = 1.8 to 3.6v 0 ? 0.3 v dd input voltage 1 (reset_n) (test0) (p00?p03) (p30?p35) (p40?p47) (p50?p53) vil1 v dd = 1.25 to 3.6v 0 ? 0.2 v dd v 5 input pin capacitance (p00?p03) (p30?p35) (p40?p47) (p50?p53) cin f = 10khz v rms = 50mv ta = 25 c ? ? 5 pf ?
fedl610403-04 ML610401/ml610402/ml610403 21/27 measuring circuits measuring circuit 1 measuring circuit 2 input pins v v dd v ddl v l1 v l2 v l3 v ss vih vil output pins (*1) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. (*2) (*1) c v : 1 f c a ,c b ,c c : 0.1 f c 12 : 0.47 f 32.768khz crystal: dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v 32.768khz crystal c gl c dl
fedl610403-04 ML610401/ml610402/ml610403 22/27 measuring circuit 3 measuring circuit 4 measuring circuit 5 input pins a v dd v ddl v l1 v l2 v l3 v ss output pins *3: measured at the specified output pins. (*3) input pins v dd v ddl v l1 v l2 v l3 v ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. (*1) waveform monitoring input pins a v dd v ddl v l2 v l3 v ss vih v l1 vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1)
fedl610403-04 ML610401/ml610402/ml610403 23/27 ac characteristics (external interrupt) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 ? 106.8 s ac characteristics (uart) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt ? ? brt* 1 ? s receive baud rate t rbrt ? brt* 1 ? 3% brt* 1 brt* 1 +3% s *1: baud rate period (including the error of the clock freq uency selected) set with the serial port baud rate register (ua0brtl,h) and the serial port mode register 0 (ua0mod0). t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) p00?p03 p50?p53 (both-edge interrupt) t nul t nul t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610403-04 ML610401/ml610402/ml610403 24/27 ac characteristics (rc oscillation a/d converter) condition for v dd =1.8 to 3.6v (v dd =1.8 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=1k ? 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k ? 53.48 58.18 62.43 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=100k ? 5.43 5.89 6.32 khz kf1 rt0, rt0-1, rt1=1k ? 7.972 9.028 9.782 ? kf2 rt0, rt0-1, rt1=10k ? 0.981 1 1.019 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k ? 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) v dd v ddl c l v ss c v rt0, rt0-1, rt1: 1k /10k /100k rs0, rs1: 10k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm frequency measurement (f oscx ) input pin vih vil *1: input logic circuit to determine the specified measuring conditions. cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1 (note 1)
fedl610403-04 ML610401/ml610402/ml610403 25/27 condition for v dd =1.25 to 3.6v (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=6k ? 81.93 93.16 101.2 khz f osc2 resistor for oscillation=15k ? 35.32 38.75 41.48 khz oscillation frequency v dd = 1.5v f osc3 resistor for oscillation=105k ? 5.22 5.65 6.03 khz kf1 rt0, rt0-1, rt1=1k ? 2.139 2.381 2.632 ? kf2 rt0, rt0-1, rt1=10k ? 0.973 1 1.028 ? rs to rt oscillation frequency ratio *1 v dd = 1.5v kf3 rt0, rt0-1, rt1=100k ? 0.142 0.147 0.152 ? f osc1 resistor for oscillation=6k ? 85.28 94.58 103.3 khz f osc2 resistor for oscillation=15k ? 35.72 38.87 41.78 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=105k ? 5.189 5.622 6.012 khz kf1 rt0, rt0-1, rt1=1k ? 2.227 2.432 2.626 ? kf2 rt0, rt0-1, rt1=10k ? 0.982 1 1.018 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k ? 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) note: - please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistor s and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. - when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have vss(gnd) trace next to the signal. - please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. rt0, rt0-1, rt1: 1k /10k /100k ra0, ra0-1, ra1: 5k rs0, rs1: 15k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf frequency measurement (f oscx ) input pin *1: input logic circuit to determine the specified measuring conditions. (note 1) v dd v ddl c l v ss c v rcm vih vil cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 in0 cvr0 cvr1 ra1 ra0-1 rt1 ra0
fedl610403-04 ML610401/ml610402/ml610403 26/27 revision history page document no. date previous edition current edition description fedl610403-01 dec.6,2010 ? ? final edition 1 3 3 change the package sample part s number 18 18 add recommended v dd pin external capacitance and add the notes about the capacitance value fedl610403-02 oct.30,2012 18 18 change v ddl pin external capacitance and add the notes about the capacitance value all all change header and footer 3 3 change from "shipment" to " product name ? supported function " 2 2 delete the description of lcd drivers 1/2 bias supported version 19 16 correct minimum time of power-on reset generated power rise time fedl610403-03 apr.18,2014 3,5,6,7 3 delete package products - 15 add clock generation circuit operating conditions 16 16 change "reset" to " reset pulse width (p rst )" and " power-on reset activation power rise time (t por )". 16 16 correct minimum time of power-on reset generated power rise time fedl610403-04 may.23,2014 16 16 correct the c gl ?s value and the c dl ?s value of dc characteristics (1/5)?s note no.2
fedl610403-04 ML610401/ml610402/ml610403 27/27 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2010-2014 lapis semiconductor co., ltd.

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